About me

Typically, you will find me curious about everything related to computer engineering, be it FPGAs, CPUs, NICs, operating systems or compilers. It is oddly satisfying to build or tune something to its maximum efficiency. And it's even better when working with other people to see it have a business impact.

Currently, I am at AMD (Cambridge, UK), helping the finance industry achieve low network latency. My day-to-day activities are all over the place. It ranges from consulting with customers to diving into Onload (kernel bypass network stack) or firmware to benchmarking and analysing bottlenecks for next-gen NICs.

In the past, I did my PhD at the University of Manchester on dynamic resource management for FPGAs in cloud/edge environments. Along the way also worked on how to build and compile modular FPGA systems just like we build and compile software applications. This resulted in FPGA Operating System (FOS).

Words I like to live by:
People of accomplishment rarely sat back and let things happen to them. They went out and happened to things. - Leonardo da Vinci

Past Work

The FOS (FPGA Operating System)

With FOS you can use the FPGA in traditional as well as multi-tenancy mode. It is built on top of modular FPGA development Flow and resource elastic scheduler for highest flexibility and performance.

Module FPGA Development Flow

Build FPGA systems that allow each system component to be swappable and agnostic to the heterogeneity of EDA tool versions, hardware and software layers.

Heterogeneous Resource Elasticity

Dynamically change the resource allocation for both FPGA and CPU transparently from the user. Including the number of compute units, workload partitioning, accelerator selection and device type selection.

Live migration for FPGA Accelerators

Transparently move an OpenCL accelerator from one FPGA to another with lower overhead.

My Journey


AMD - Senior Product Applications Engineer

Part of NIC Applications Engineer team.

Aug 2021 - Present

Cohst.Me - Co-Founder

Worked on SaaS platform for Infulencer Marketing and Monetisation for Video Services

May 2020 - July 2021

PhD in Computer Science

At The University of Manchester, on Resource Management & FPGA Virtualisation as a President's Doctoral Scholar. Read my PhD thesis.

Sep 2017 - Aug 2020

Multi-tenant FPGA Platform Designer

Designed The FOS (FPGA Operating System) and presented the demo live at FPL 2019. Find it online on GitHub.

Jun 2019 - Sep 2019

HTV - Consulting Embedded Platform Engineer

Developed an embedded platform with remote-access for cryptography acceleration on FPGAs.

Sept 2018 - Nov 2018

BEng (Hons) Computer Systems Engineering

At Univesity of Manchester with specialisation in Computer Architecture and System on Chip. Read my final year thesis.

Sept 2014 - July 2017

ARM - Hardware Intern - Design and Verification

Part of Verification IP team working on AMBA protocols (CHI, ACE, AXI) and its future variants.

July 2016 - Sept 2016

Summer Research Assistant

Worked on Transport triggered and Dataflow Computer Architecture under Dr. Javier Navaridas.

July 2015 - Aug 2015


Find the complete list on Google Scholar.


Honours and Awards

Other Interests

Get In Touch